1. Field of the Invention
The present invention relates to a method for forming a complementary metal-oxide semiconductor (CMOS) transistor, and more particularly, to a method for forming a CMOS transistor which can prevent short channel effects.
2. Description of the Prior Art
With the increasing component density of semiconductor devices, CMOS transistors, which consume less energy, are widely used in ultra-large scale integrated (ULSI) designs. A CMOS transistor is composed of two complementary transistors, which are a PMOS transistor and an NMOS transistor. There are typically three different types of the CMOS transistors: P-well CMOS transistors, N-well CMOS transistors and twin well CMOS transistors. When the line width of a semiconductor device is less than 1 .mu.m, due to resulting electrical characteristics, twin well CMOS transistors become the elements of choice in circuit designs. Therefore, improving the CMOS manufacturing process to increase the performance of CMOS devices, and twin well CMOS devices in particular, is an important issue in the semiconductor industry.
Please refer to FIG. 1 and FIG. 2. FIG. 1 and FIG. 2 are cross sectional diagrams of a prior art method for forming a CMOS transistor 36 on a semiconductor wafer 10. As shown in FIG. 1, a semiconductor wafer 10 comprises a silicon substrate 12, a p-well 14 positioned on the substrate 12, an n-well 16 positioned on the substrate 12 adjacent to the p-well 14, a gate 20 positioned on the p-well 14 to form an NMOS transistor 33 of the CMOS transistor 36, a gate 21 positioned on the n-well 16 to form a PMOS transistor 34 of the CMOS transistor 36, and a field oxide layer 18 positioned on the p-well 14 and the n-well 16 around the gates 20 and 21, serving as an insulation layer.
In the prior art method for forming the CMOS transistor 36, using the gates 20, 21 as hard masks, two ion implantation processes are performed adjacent to and abutting the gates 20, 21 so as to form an n-type doped region 22 on the p-well 14 and a p-type doped region 24 on the n-well 16. The doped regions 22, 24 serve as heavy doped drains (HDD) of the NMOS transistor 33 and the PMOS transistor 34, respectively. Chemical vapor deposition (CVD) processes are then performed to form a silicon oxide layer and a silicon nitride layer on the semiconductor wafer 10. A dry etching process is performed to remove the silicon oxide layer and the silicon nitride layer down to the surface of the p-well 14 and the n-well 16. The residual silicon oxide layers and silicon nitride layers on each of the two lateral surfaces of each of the gates 20, 21 form liner oxides 26 and spacers 28. Then, using the gates 20, 21 and the spacers 28 as hard masks, two ion implantation processes are performed adjacent to and abutting the spacers 28 so as to form an n-type doped region 30 on the p-well 14 and a p-type doped region 32 on the n-well 16. The doped regions 30, 32 serve as sources/drains of the NMOS transistor 33 and the PMOS transistor 34, as shown in FIG. 2.
Please refer to FIG. 3. FIG. 3 is a cross sectional diagram of a prior art CMOS transistor 36 in which the doped regions 30, 32 and the HDD 22, 24 have become diffused. After the formation of the CMOS transistor 36, thermal processes may be performed on the semiconductor wafer 10, such as the formation of a self-aligned silicide (salicide) layer on the gates 20, 21 and the source/drain. These thermal processes will result in diffusion of the dopants in the HDD 20, 22 and in the doped regions 30, 32. This results in a decrease of the designed channel length of the transistor. In the method for forming the prior art CMOS transistor 36, the doped areas of the HDD 22, 24 are adjacent to the gates 20, 21. The diffusion rates of p-type dopants (such as boron or BF.sub.2.sup.+) are faster than those of n-type dopants (such as phosphorous or arsenic), and so the reduced channel length is more obvious in the PMOS transistor 34. Furthermore, short channel effects may occur in the CMOS transistor 36. Additionally, when the doped region 32 of the PMOS transistor 34 has been diffused, the area of the drain under the gate 21 increases, which may result in an overlap capacitance between the gate and the drain. Such capacitances increase the RC time, affecting the electrical performance of the CMOS transistor.